In conventional CMOS designs, snap-back and latch-up mechanisms have always been an operational concern. The snap-back mechanism is discussed by Ochoaw Jr. et al in their paper Snap-Back: A Stable Regenerative Breakdown Mode For MOS Devices, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, Vol. NS-30 No. 6, December 1983; Lee et al in U.S. Pat. No. 5,270,565. The latch-up mechanism is discussed by Mazure et al in their paper Improvement Of Latch-Up Hardness By Geometry And Technology Tuning, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 35, No. 10, October 1988; by Hidaka in U.S. Pat. No. 5,212,616. Both snap-back and latch-up, if triggered and left unchecked, will cause irreversible damage to circuit as well as to the component itself.
Snap-back and latch-up exist in CMOS components due to the existence of parasitic bipolar transistors. To illustrate the first scenario of snap-back, a conventional NMOS transistor 10 is depicted in FIG. 1. The transistor 10 has a P-well 12 formed in a silicon layer 14, an n+ drain region 16, p+ well region 18 and an n+ source region 20 formed in the P- well 12 and a gate 22. The gate 22 may be a metal or polysilicon insulated from the upper surface of the silicon substrate 12 by an insulator layer 24.
The hole current, h, generated by an external stimulus near the drain junction seeks the nearest p+ region 18 because the p+ region 18 is at the lowest hole potential. In the NMOS circuit, this lowest potential is provided by the V.sub.ss supply as indicated. The external stimulus may be breakdowns caused by overvoltage transients, electrostatic discharge (ESD) light excitation or other unpredictable occurrences.
A superimposed parasitic npn transistor 26, as shown in FIG. 2, will be turned on if the hole current h is large enough to generate a potential difference of over 0.5 volts across the n+/p-well junction AA'. This action is regenerative because more electrons (e) will be injected from the n+ source region 20 to render yet more holes to be supplied from the impact ionization in the source-well depletion region DD'. Once triggered, this parasitic current will create local hot spots. If the intrinsic temperature of the silicon layer is exceeded, the formation of mesoplasmas will eventually cause the surrounding material to melt. The NMOS transistor will be destroyed unless the transistor goes through a power down cycle. The prior art cited above teaches additional circuit components that can be designed into an integrated circuit to detect a current surge and initiate a power down cycle.
In latch-up, on the other hand, an NMOS transistor 28 and a PMOS transistor 30 are involved as shown on FIGS. 3 and 4.
The NMOS transistor 28 consists of a P-well 32 formed in a silicon substrate and further has an n+ drain region 34, an n+ source region 36, a p+ well region 38 adjacent to the n+source region 36 and a gate 40 formed on an insulating layer 42. The PMOS transistor 30 has an n- well 44 formed in the silicon substrate and further has a p+ drain region 46, a p+ source region 48, an n+ well region 50 adjacent to the p+ source region 48, and a gate 52 provided on top of an insulating layer 54.
In the NMOS transistor 28, the stray hole current (h) generated by an overvoltage, overcurrent, a rapid change in voltage (dv/dt), excessive ambient temperature, or a combination of some or all of these conditions, will seek the nearest p+ region such as p+ well 38. This is illustrated by the superimposed circuit in which the hole current (h+) flows from the P- well 32 through a resistance RW1 past point A, through a resistance RP to a point C in the p+ well region 38. Again, when the voltage between point A and a point A' in the n+ source region 36 exceeds 0.5 volts, a parasitic npn transistor 56 will be formed as shown in FIG. 4. The stray electron current (e-) generated in the n-well 44 by an overvoltage, overcurrent, a rapid change in voltage (dv/dt) excessive ambient temperature or a combination of some or all of these conditions will seek the nearest n+ region and in particular n+ well region 50. This is illustrated by the superimposed circuit in which the electrons flow from the n-well 44 through a resistance RW2 past point B, through resistance RN to the n+ well region 50 illustrated by point F. Again, when the voltage between point B and the p+ source region 49 illustrated as point B' exceeds 0.5 volts a thyristor 58 will be formed. If the reverse bias at the two junctions formed by points AA' and BB' is greater than 0.5 volts, a regenerative action, called latch-up, involving parasitic thyristors 56 and 58 will occur and the destruction of the CMOS device comprising NMOS transistor 28 and PMOS transistor will soon follow.
The rugged output stage structure of this invention improves the snap-back and latch-up thresholds beyond the full power supply voltage range and will only slightly increase the size of the stage structure.